Wirebond recess for stacked die

摘要

A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack.

主权项

1. A semiconductor device package comprising:
a first semiconductor device die comprising a first major surface and a second major surface opposite and having a substantially parallel plane to the first major surface, wherein the first major surface comprises a first bond pad; a wire bond coupled to the first bond pad, wherein
the wire bond comprises a bond in contact with the first bond pad and a wire bond loop extending a vertical height from the bond and a horizontal distance from the bond over the first major surface of the first semiconductor device die; and a second semiconductor device die comprising a first major surface and a second major surface opposite and having a substantially parallel plane to the first major surface, wherein
the second major surface of the second semiconductor device die is attached to the first major surface of the first semiconductor device die,the second major surface of the second semiconductor device die comprises a notch structure in a region above the first bond pad of the first semiconductor device die and the wire bond coupled to the first bond pad,the wire bond clears the second semiconductor device die by virtue of being within the notch structure,a length and width of the notch structure are less than corresponding dimensions of the second semiconductor device die, andthe notch structure provides a surface in the second semiconductor device die extending to a depth within the second semiconductor device die greater than or equal to the vertical height of the wire bond loop, a length along the second major surface of the second semiconductor device die greater than or equal to the horizontal distance of the wire bond loop over the first major surface of the first semiconductor device die, and a width along the second major surface of the second semiconductor device die greater than a width of the bond and less than a parallel dimension of the second semiconductor device die.