Unit cells of nonvolatile memory devices, cell arrays of nonvolatile memory devices, and methods of fabricating the same

摘要

Unit cells including a substrate having an active region, a first charge trap pattern disposed on the substrate to intersect the active region, a second charge trap pattern disposed on the substrate to intersect the active region and spaced apart from the first charge trap pattern, a first junction region disposed in the active region between the first and second charge trap patterns, a second junction region disposed in the active region adjacent to one side of the first charge trap pattern opposite to the second charge trap pattern, and a third junction region disposed in the active region adjacent to one side of the second charge trap pattern opposite to the first charge trap pattern.

主权项

1. A unit cell of a nonvolatile memory device, the unit cell comprising:
a substrate having an active region; a first charge trap pattern disposed on the substrate to intersect the active region; a second charge trap pattern disposed on the substrate to intersect the active region and spaced apart from the first charge trap pattern; a first junction region disposed in the active region between the first and second charge trap patterns; a second junction region disposed in the active region adjacent to one side of the first charge trap pattern opposite to the second charge trap pattern and spaced apart from the first junction region by a first planar channel region; and a third junction region disposed in the active region adjacent to one side of the second charge trap pattern opposite to the first charge trap pattern and spaced apart from the first junction region by a second planar channel region, wherein the first charge trap pattern includes a first tunneling laver, a first charge trap layer, a first insulation layer and a first control gate layer which are sequentially stacked, wherein the first planar channel region between the first junction region and the second junction region is entirely overlapped with the first charge trap layer, wherein the second charge trap pattern includes a second tunneling layer, a second charge trap layer, a second insulation layer and a second control gate layer which are sequentially stacked, and wherein the second planar channel region between the first junction region and the third junction region is entirely overlapped with the second charge trap layer.