发明名称 |
Reliable, low latency hardware and software inter-process communication channel for safety critical system |
摘要 |
A fault-tolerant failsafe computer system including an inter-processor communication channel includes a transmission control module that encodes a first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet. The system also includes a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet and ii) decodes the first encoded copy and the second encoded copy. The system further includes a de-duplication module that receives a plurality of data packets and communicates at least one unique data packet of the plurality of data packets. |
申请公布号 |
US9317359(B2) |
申请公布日期 |
2016.04.19 |
申请号 |
US201414219051 |
申请日期 |
2014.03.19 |
申请人 |
Artesyn Embedded Computing, Inc. |
发明人 |
Vaananen Pasi Jukka Petteri;Cornes Martin Peter John |
分类号 |
H04L1/18;G06F11/10;H04L1/00;H04L1/08 |
主分类号 |
H04L1/18 |
代理机构 |
Harness, Dickey & Pierce, P.L.C. |
代理人 |
Harness, Dickey & Pierce, P.L.C. |
主权项 |
1. A fault-tolerant failsafe computer system including an inter-processor communication channel comprising:
a multiplexer that receives a plurality of incoming data packets from a plurality of components of the fault-tolerant failsafe computer system and selectively communicates a first data packet; a transmission control module receiving the first data packet and encodes the first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet; a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet and ii) decodes the first encoded copy and the second encoded copy; a de-duplication module that receives a plurality of data packets from the receiver control module and communicates at least one unique data packet of the plurality of data packets; and a de-multiplexer that receives the at least one unique data date packet from the de-duplication module and selectively communicates the at least one unique data packet to the plurality of components of the fault-tolerant failsafe computer system. |
地址 |
Tempe AZ US |