发明名称 Internal voltage generation circuits
摘要 Internal voltage generation circuits are provided. The internal voltage generation circuit includes a drive controller and an initialization unit. The drive controller detects a level of an internal voltage signal in response to a reference voltage signal to generate a drive signal and drives the internal voltage signal in response to the drive signal. The initialization unit initializes the drive signal in synchronization with an internal command signal and terminates an initialization of the drive signal during a predetermined period.
申请公布号 US9317051(B2) 申请公布日期 2016.04.19
申请号 US201414174046 申请日期 2014.02.06
申请人 SK hynix Inc. 发明人 Kwon Ig Soo
分类号 G05F1/46;G11C5/14;G11C7/20 主分类号 G05F1/46
代理机构 William Park & Associates Ltd. 代理人 William Park & Associates Ltd.
主权项 1. An internal voltage generation circuit comprising: a drive controller suitable for detecting a level of an internal voltage signal in response to a reference voltage signal to generate a drive signal and driving the internal voltage signal in response to the drive signal; and an initialization unit suitable for initializing the drive signal in synchronization with an up-command signal and a down-command signal and terminating an initialization of the drive signal during a predetermined period from a point of time that the drive signal is initialized, wherein the up-command signal includes at least one pulse for executing any one among an active operation, a read operation and a write operation of a first memory cell array and wherein the down-command signal includes at least one pulse for executing any one among an active operation, a read operation and a write operation of a second memory cell array, wherein the initialization unit includes a command synthesizer suitable for synthesizing the up-command signal and the down-command signal to generate an internal command signal and a level signal generator suitable for generating a level signal whose logic level is changed in response to the internal command signal, wherein the logic level of the level signal is changed whenever at least two pulses of the internal command signal is generated.
地址 Icheon-si Gyeonggi-do KR