Digital PLL with hybrid phase/frequency detector and digital noise cancellation

摘要

Digital phase-locked loop (PLL) with dynamic hybrid (mixed analog/digital signal) delta-sigma (ΔΣ) phase/frequency detector (ΔΣ PFD). A hybrid 2nd-order ΔΣ PFD may be implemented based on a continuous-time 1st-order ΔΣ analog-to-digital converter (ADC) enhanced to 2nd-order via closed loop frequency detection. Fine resolution encoding of the ΔΣ PFD output facilitates true multi-bit phase/frequency error digitization with drastically reduced ΔΣ quantization noise. The implementation of low complexity ΔΣ PFD is assisted via digital requantization and adaptive noise cancellation. The PLL includes independent frequency-locking and phase-locking operational modes and all-digital control of a digitally controlled oscillator (DCO).

主权项

1. A phase locked-loop (PLL) comprising:
a digitally controlled oscillator (DCO) configured to generate a DCO output frequency in response to a tuning input; a frequency reference oscillator configured to generate a reference frequency input; a mixed analog/digital signal Delta-Sigma (ΔΣ) Phase/Frequency Detector (ΔΣ PFD) configured to generate a digital output of frequency difference between the reference frequency input and the DCO frequency output, the ΔΣ PFD comprising:
a digital requantizer configured to change a quantization resolution of a feedback portion of the digital output; anda feedback path configured to receive the feedback portion after the quantization resolution is changed; an accumulator configured to generate digital phase and frequency error information by accumulating the ΔΣ PFD digital output combined with a digital indicator of a targeted output frequency for the DCO; and a loop filter following the accumulator and configured to tune phase/frequency of the DCO in response to digital phase and frequency error information.