发明名称 |
Apparatus, method and system to determine memory access command timing based on error detection |
摘要 |
Techniques and mechanisms to dynamically adjustment a timing of commands to access a dynamic random access memory (DRAM). In an embodiment, a memory controller monitors an error rate of the DRAM and, based on such monitoring, identifies that the error rate is within a predetermined range. In response to the error rate being within the predetermined range, one or more signals are generated to dynamically modify a command timing setting. In another embodiment, modification of the command timing setting is to transition a memory controller from sending memory refresh commands successively at one rate to sending memory refresh commands successively at a different rate. |
申请公布号 |
US9318182(B2) |
申请公布日期 |
2016.04.19 |
申请号 |
US201314139558 |
申请日期 |
2013.12.23 |
申请人 |
Intel Corporation |
发明人 |
Lovelace John V. |
分类号 |
G11C11/40;G11C11/406;G11C29/02;G11C29/42;G11C29/50;G11C29/04 |
主分类号 |
G11C11/40 |
代理机构 |
Blakely, Sokoloff, Taylor & Zafman LLP |
代理人 |
Blakely, Sokoloff, Taylor & Zafman LLP |
主权项 |
1. A memory controller comprising:
command logic to generate first commands to access a dynamic random access memory (DRAM) coupled to the memory controller, including the command logic to generate the first commands according to a first timing; and detect logic to monitor an error rate of the DRAM and to send to a basic input output system (BIOS) an indication of the error rate, wherein based on the indication, the BIOS to identify that the error rate is within a predetermined range and generates one or more signals in response to the error rate being within the predetermined range, the one or more signals to dynamically modify a command timing setting to transition from the first timing to a second timing, wherein, based on the one or more signals, the command logic to generate second commands according to the second timing, the second commands to access the DRAM. |
地址 |
Santa Clara CA US |