发明名称 |
Bit line equalizing circuit |
摘要 |
There is provided a bit line equalizing circuit including: an active region; a first bit line disposed on the active region in a first direction; a second bit line disposed on the active region in the first direction; a gate pattern including a first pattern disposed on the active region in a second direction crossing the first direction, and a second pattern extended from one side of the first pattern to be disposed in the first direction, and formed in a stair shape; a first contact disposed at one side of the first pattern and one side of the second pattern, and configured to connect the active region and the first bit line; a second contact disposed at one side of the first pattern and the other side of the second pattern, and configured to connect the active region and the second bit line; and a third contact disposed at the other side of the first pattern, and configured to provide a predetermined voltage to the active region. |
申请公布号 |
US9318169(B2) |
申请公布日期 |
2016.04.19 |
申请号 |
US201414326543 |
申请日期 |
2014.07.09 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
Won Bok-Yeon;Kwon Hyuk-Joon |
分类号 |
G11C7/00;G11C7/12;G11C11/4094;H01L27/02;H01L27/108 |
主分类号 |
G11C7/00 |
代理机构 |
Sughrue Mion, PLLC |
代理人 |
Sughrue Mion, PLLC |
主权项 |
1. A bit line equalizing circuit comprising:
an active region; a first bit line disposed on the active region in a first direction; a second bit line disposed on the active region in the first direction; a gate pattern including a first pattern disposed on the active region in a second direction crossing the first direction, and a second pattern extended from one side of the first pattern to be disposed in the first direction, the second pattern being formed in a stair shape on the active region; a first contact disposed at one side of the first pattern and one side of the second pattern, and configured to connect the active region and the first bit line; a second contact disposed at one side of the first pattern and the other side of the second pattern, and configured to connect the active region and the second bit line; and a third contact disposed at the other side of the first pattern, and configured to provide a predetermined voltage to the active region. |
地址 |
Suwon-si KR |