发明名称 |
Cache memory apparatus, cache control method, and microprocessor system |
摘要 |
A cache memory apparatus according to the present invention includes a cache memory that caches an instruction code corresponding to a fetch address and a cache control circuit that controls the instruction code to be cached in the cache memory. The cache control circuit caches an instruction code corresponding to a subroutine when the fetch address indicates a branch into the subroutine and disables the instruction code to be cached when the number of the instruction codes to be cached exceeds a previously set maximum number. |
申请公布号 |
US9317438(B2) |
申请公布日期 |
2016.04.19 |
申请号 |
US201213668009 |
申请日期 |
2012.11.02 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
Kitahara Takashi |
分类号 |
G06F12/00;G06F12/08;G06F9/38 |
主分类号 |
G06F12/00 |
代理机构 |
McDermott Will & Emery LLP |
代理人 |
McDermott Will & Emery LLP |
主权项 |
1. A cache memory apparatus comprising;
a cache memory that caches an instruction code corresponding to a fetch address; and a cache control circuit that controls the instruction code to be cached in the cache memory, wherein the cache control circuit:
caches the instruction code corresponding to a subroutine when the fetch address indicates a branch into the subroutine, anddisables the instruction code to be cached when a number of instruction codes to be cached exceeds a previously set maximum number; and wherein the previously set maximum number of the instruction codes is obtained by dividing a number of clocks since a CPU outputs the fetch address to a memory until the memory outputs the instruction code by a number of clocks necessary for the CPU to execute one instruction code. |
地址 |
Tokyo JP |