Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline

摘要

A microprocessor includes a plurality of processing cores each including a hardware instruction translator that translates instructions of x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs into microinstructions defined by a microinstruction set of the microprocessor. The microinstructions are encoded in a distinct manner from the manner in which the instructions of the x86 and ARM instruction sets are defined. Each core includes an execution pipeline that executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. Each core uses and associated indicator to determine whether it will boot as an x86 ISA core or an ARM ISA core when reset. The indicators are configurable to indicate that at least one of the cores will boot as an x86 ISA core and at least one other of the cores will boot as an ARM ISA core.

主权项

1. A microprocessor, comprising:
a plurality of processing cores, each of the processing cores comprising:
a hardware instruction translator, that translates instructions of x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs into microinstructions defined by a microinstruction set of the microprocessor, wherein the microinstructions are encoded in a distinct manner from the manner in which the instructions defined by the instruction sets of the x86 ISA and ARM ISA are encoded;an execution pipeline, coupled to the hardware instruction translator, wherein the execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions;an instruction cache, that holds the x86 ISA and ARM ISA instructions and provides them directly to the hardware instruction translator; andwherein the hardware translator comprises:
an instruction formatter configured to extract x86 ISA and ARM ISA instructions from the instruction cache, to pre-decode instruction bytes as x86 instruction bytes or ARM instruction bytes, and to indicate each instruction byte as a start byte, an end byte, and/or a valid byte of an ISA instruction;a simple instruction translator including an x86 simple instruction translator to translate pre-decoded x86 instructions from the instruction formatter and an ARM simple instruction translator to translate pre-decoded ARM instructions from the instruction formatter; anda complex instruction translator to translate a subset of x86 instructions and a subset of ARM instructions.