发明名称 |
Floating point multiply-add unit with denormal number support |
摘要 |
The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum. |
申请公布号 |
US9317250(B2) |
申请公布日期 |
2016.04.19 |
申请号 |
US201213674220 |
申请日期 |
2012.11.12 |
申请人 |
Advanced Micro Devices, Inc. |
发明人 |
Goveas Kelvin D.;Sarma Debjit Das;Hilker Scott A.;Liu Hanbing |
分类号 |
G06F7/483;G06F7/499;G06F7/544 |
主分类号 |
G06F7/483 |
代理机构 |
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代理人 |
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主权项 |
1. A floating point multiply-add unit (FMAC) configurable to add a product of first and second operands to a third operand, wherein the FMAC comprises:
a minimum exponent determination hardware module to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product; and a left shift hardware module to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum. |
地址 |
Sunnyvale CA US |