Enhanced multi-processor waveform data exchange using compression and decompression

摘要

Configurable compression and decompression of waveform data in a multi-core processing environment improves the efficiency of data transfer between cores and conserves data storage resources. In waveform data processing systems, input, intermediate, and output waveform data are often exchanged between cores and between cores and off-chip memory. At each core, a single configurable compressor and a single configurable decompressor can be configured to compress and to decompress integer or floating-point waveform data. At the memory controller, a configurable compressor compresses integer or floating-point waveform data for transfer to off-chip memory in compressed packets and a configurable decompressor decompresses compressed packets received from the off-chip memory. Compression reduces the memory or storage required to retain waveform data in a semiconductor or magnetic memory. Compression reduces both the latency and the bandwidth required to exchange waveform data. This abstract does not limit the scope of the invention as described in the claims.

主权项

1. A system for processing waveform data, wherein the waveform data comprise samples represented in an integer data format or a floating-point data format, comprising:
a plurality of processor cores and a communications fabric for transfer of data packets among the plurality of processor cores; compression logic integrated with a source processor core of the plurality of processor cores, wherein the compression logic is operable to compress a plurality of samples from the source processor core in accordance with one or more compression control parameters to form a plurality of compressed samples, the compression logic further including logic to provide the compressed samples to a data portion of a compressed packet and the one or more compression control parameters to a header portion of the compressed packet for transmission on the communication fabric; and decompression logic integrated with a destination processor core of the plurality of processor cores, wherein the decompression logic is applied to the compressed packet received from the communication fabric to decompress the compressed samples from the data portion of the compressed packet in accordance with the one or more compression control parameters from the header portion of the compressed packet to form a plurality of decompressed samples.