Instruction set architecture mode dependent sub-size access of register with associated status indication

摘要

A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.

主权项

1. A processor comprising:
a physical register file comprising a plurality of physical registers configured to store data associated with a plurality of data types corresponding to at least two different sizes; and control circuitry; wherein the control circuitry is configured to:
store an indication of a mode of at least two modes in a register;access said register to detect the mode of at least two modes that indicates whether instructions corresponding to a first instruction set architecture (ISA) are being processed or instructions corresponding to a second ISA different from the first ISA are being processed, wherein the first ISA does not support data operands with a size equal to a full size of a register of the plurality of registers and the second ISA does support data operands with a size equal to the full size of a register of the plurality of registers;in response to detecting a first mode of the at least two modes, determine a first instruction is associated with the first ISA, allow access to a first portion of a given register of the plurality of physical registers identified by the first instruction and prevent access to a second portion of the given register;in response to detecting a second mode of the at least two modes, determine the first instruction is associated with the second ISA and allow access to the full size of the given register; andin response to detecting the first mode and the given register is a destination register for the first instruction, store a first indication corresponding to the given register that indicates the given register is being used to store a data operand associated with the first ISA.