发明名称 |
Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) having a ferroelectric capacitor aligned with a three dimensional transistor structure |
摘要 |
A method for a non-volatile, ferroelectric random access memory (F-RAM) device that includes a ferroelectric capacitor aligned with a preexisting structure is described. In one embodiment, the method includes forming an opening in an insulating layer over a contact in a planar surface of a substrate to expose at least a portion of the contact. Next a self-aligned contact (SAC) is formed electrically coupling to the contact, the SAC medially located in the opening and proximal to a sidewall thereof. A ferroelectric spacer is then formed in the opening medially of the SAC, and a top electrode spacer formed in the opening over the insulating cap and medially of the ferroelectric spacer. |
申请公布号 |
US9318693(B2) |
申请公布日期 |
2016.04.19 |
申请号 |
US201314010174 |
申请日期 |
2013.08.26 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
Cronin John;Sun Shan;Davenport Thomas |
分类号 |
H01L21/00;H01L43/02;H01L27/115;H01L27/22 |
主分类号 |
H01L21/00 |
代理机构 |
|
代理人 |
|
主权项 |
1. A method comprising:
forming an opening in an insulating layer over a contact in a planar surface of a substrate to expose at least a portion of the contact; forming a self-aligned contact (SAC) electrically coupling to the contact, the SAC medially located in the opening and proximal to a sidewall thereof; forming an insulating cap in a lower portion of the opening, the insulating cap on an exposed portion of the contact; forming a ferroelectric spacer in the opening medially of the SAC and on said insulating cap; and forming a top electrode spacer in the opening medially of the ferroelectric spacer and on said insulating cap. |
地址 |
San Jose CA US |