Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices

摘要

One illustrative method disclosed herein includes, among other things, forming a first epi semiconductor material in a source/drain region of a transistor device, the first epi semiconductor material having a first lateral width at an upper surface thereof, forming a second epi semiconductor material on the first epi semiconductor material and above at least a portion of one of a gate cap layer or one of the sidewall spacers of the device, wherein the second epi semiconductor material has a second lateral width at an upper surface thereof that is greater than the first lateral width, and forming a metal silicide region on the upper surface of the second epi semiconductor material.

主权项

1. A method of forming a transistor device comprising a gate structure, a gate cap layer positioned above said gate structure and a sidewall spacer positioned on opposite sidewalls of said gate structure, the method comprising:
forming a first epi semiconductor material in a source/drain region of said transistor device, said first epi semiconductor material directly contacting a channel region of said transistor device and having a first lateral width at an upper surface thereof; forming a second epi semiconductor material on said first epi semiconductor material and above at least a portion of one of said gate cap layer or one of said sidewall spacers, said second epi semiconductor material extending laterally over and covering at least a portion of an uppermost end of said sidewall spacer and having a second lateral width at an upper surface thereof that is greater than said first lateral width; and forming a metal silicide region on the upper surface of said second epi semiconductor material.