发明名称 Method for manufacturing semiconductor device
摘要 As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.
申请公布号 US9318512(B2) 申请公布日期 2016.04.19
申请号 US201514694212 申请日期 2015.04.23
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Miyairi Hidekazu;Osada Takeshi;Yamazaki Shunpei
分类号 H01L21/477;H01L27/12;H01L29/24;H01L29/786;H01L29/417;H01L29/423;H01L29/66 主分类号 H01L21/477
代理机构 Robinson Intellectual Property Law Office 代理人 Robinson Intellectual Property Law Office ;Robinson Eric J.
主权项 1. A method for manufacturing a semiconductor device, comprising: forming a first conductive film that serves as a first gate electrode of a transistor over a substrate; forming a first insulating film over the first conductive film; forming an oxide semiconductor layer that comprises a channel formation region over the first insulating film; forming a second insulating film over the oxide semiconductor layer; and forming a transparent film that comprises an oxide including indium and zinc over the second insulating film by a sputtering method, wherein the transparent film serves as a second gate electrode of the transistor, wherein the first conductive film and the transparent film overlap each other with the oxide semiconductor layer therebetween, and wherein the transparent film has a larger width than the oxide semiconductor layer in a channel width direction of the transistor.
地址 Kanagawa-ken JP
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