Shift register and method of controlling the shift register

摘要

A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

主权项

1. A shift register comprising:
a plurality of shift register units, wherein at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, and the at least one shift register unit comprises: a signal input circuit electrically coupled to the forestage shift register unit and configured for receiving a logic signal from the forestage shift register, wherein the signal input circuit comprises:
a first inverter having an input terminal for receiving the logic signal from the forestage shift register; anda first transistor having a gate electrically coupled to the input terminal of the first inverter, a first terminal electrically coupled to an output terminal of the first inverter, and a second terminal; a signal output circuit electrically coupled to the signal input circuit and the post-stage shift register unit and configured for receiving a first clock signal, wherein the signal output circuit is electrically coupled to the signal input circuit via a control signal terminal, wherein the control signal terminal is electrically coupled to the second terminal of the first transistor, and the signal output circuit comprises:
a second transistor having a gate electrically coupled to the control signal terminal, a first terminal for receiving the first clock signal, and a second terminal electrically coupled to the post-stage shift register unit; anda second inverter having an input terminal electrically coupled to the second terminal of the second transistor, and an output terminal; a pull down circuit electrically coupled to the signal input circuit and the signal output circuit and configured for receiving a first operation voltage to pull down a voltage of the control signal terminal, wherein the pull down circuit is electrically coupled to the output terminal of the second inverter, and comprises:
a third transistor having a gate electrically coupled to the input terminal of the first inverter, a first terminal electrically coupled to the output terminal of the second inverter, and a second terminal; anda fourth transistor having a gate electrically coupled to the second terminal of the third transistor, a first terminal electrically coupled to the first operation voltage, and a second terminal; and a switching circuit, electrically coupled to the second terminal of the fourth transistor, and electrically coupled between the pull down circuit and the control signal terminal, wherein the switching circuit is configured to be a current route itself to let a current flow through the switching circuit then flow through the pull down circuit when the pull down circuit pulling down the voltage of the control signal terminal.