Gate substitution based system and method for integrated circuit power and timing optimization

摘要

A processing device can identify gates of an integrated circuit design having a slack value less than a predefined slack threshold. The processing device can further, for each of the identified gates, determine (i) a number of nodes of the integrated circuit design that experience a timing slack improvement if the gate is swapped with an alternative implementation having a reduced delay or (ii) a sum of timing slack improvements experienced by nodes of the integrated circuit design if the gate is swapped with the alternative implementation having a reduced delay. The processing device can still further swap the gate with the alternative implementation having the reduced delay if the determined number or sum is greater than a corresponding predetermined threshold.

主权项

1. A system for selecting gates for an integrated circuit design comprising:
at least one processing device configured to (I) identify gates of the integrated circuit design having a slack value less than a predefined slack threshold; and (II) for each of the identified gates, determine (i) a number of nodes of the integrated circuit design that experience a timing slack improvement if an identified gate is swapped with an alternative implementation having a reduced delay or (ii) a sum of timing slack improvements experienced by nodes of the integrated circuit design if an identified gate is swapped with the alternative implementation having a reduced delay, and (III) swap the gate with the alternative implementation having the reduced delay if the determined number or sum is greater than a corresponding predetermined threshold.