发明名称 Semiconductor device and processor system including the same
摘要 Provided is a semiconductor device including: a plurality of processing circuits; an arbitration circuit that arbitrates a plurality of data transfer requests issued by the plurality of processing circuits; a mask control circuit that loads the plurality of data transfer requests arbitrated by the arbitration circuit, and sequentially outputs the plurality of data transfer requests after a lapse of a mask period; and a memory controller that accesses a memory based on the plurality of data transfer requests sequentially output from the mask control circuit, and switches a mode of the memory to a power saving mode when no data transfer request is output from the mask control circuit for a predetermined period.
申请公布号 US9317219(B2) 申请公布日期 2016.04.19
申请号 US201414228238 申请日期 2014.03.27
申请人 RENESAS ELECTRONICS CORPORATION 发明人 Kawakita Daisuke;Hori Toshikazu
分类号 G06F3/06;G06F13/36 主分类号 G06F3/06
代理机构 Shapiro, Gabro and Rosenberger, PLLC 代理人 Shapiro, Gabro and Rosenberger, PLLC
主权项 1. A semiconductor device comprising: a plurality of processing circuits; an arbitration circuit that arbitrates a plurality of data transfer requests issued by the plurality of processing circuits; a mask control circuit that loads the plurality of data transfer requests arbitrated by the arbitration circuit, and sequentially outputs the plurality of data transfer requests after a lapse of a mask period; and a memory controller that accesses a memory based on the plurality of data transfer requests sequentially output from the mask control circuit, and switches a mode of the memory to a power saving mode when no data transfer request is output from the mask control circuit for a predetermined period, wherein the mask control circuit comprises a mask signal generation circuit that generates a mask signal, the mask signal being periodically switched between an active state and an inactive state; anda transfer request output circuit coupled to the arbitration circuit which receives the mask signal that sequentially outputs the plurality of loaded data transfer requests to the memory controller when the mask signal is in the inactive state.
地址 Tokyo JP