发明名称 |
CLOCK SUPPLY SYSTEM, CLOCK SUPPLY DEVICE, AND CLOCK SUPPLY METHOD |
摘要 |
PROBLEM TO BE SOLVED: To suppress a phase jump in a clock supply system when performing switching from an act system to a standby system.SOLUTION: Distribution circuits 211 output a 0 system clock and 1 system clock received from an upper rank supply device to respective selectors 212. A synchronization circuit 213 performs phase synchronization between a clock output from each selector 212 and a clock output from a SW 215. An extraction circuit 214A0 and extraction circuit 214A1 extract reference clocks from the 0 system clock and 1 system clock, respectively. A control system makes respective SW 215 perform switching between a reference clock extracted by the extraction circuit 214A0 and a reference clock extracted by the extraction circuit 214A1 of 1 system and switching between a reference clock extracted by the extraction circuit 214A1 and a reference clock extracted by the extraction circuit 214A0 to select a reference clock of 0 system or 1 system for synchronization with a reference clock extracted from each clock.SELECTED DRAWING: Figure 4 |
申请公布号 |
JP2016054338(A) |
申请公布日期 |
2016.04.14 |
申请号 |
JP20140178363 |
申请日期 |
2014.09.02 |
申请人 |
FUJITSU LTD |
发明人 |
KIKUCHI HIDEYUKI;NAKADE HIROSHI;SUGAWARA AKIRA;KONDO RYUICHI |
分类号 |
H04L7/00;H04L1/22;H04L7/033 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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