发明名称 Multi-Stage Sample and Hold Circuit
摘要 A circuit may include a first sample node configured to provide a low precision sample of an input signal, a second sample node configured to store a high precision sample of an input signal, and a first switch circuit coupled between an input and the first sample node. The circuit may further include a second switch circuit coupled between the first sample node and the second sample node and configured to limit leakage current that could discharge the second sample node.
申请公布号 US2016104543(A1) 申请公布日期 2016.04.14
申请号 US201414511085 申请日期 2014.10.09
申请人 Silicon Laboratories Inc. 发明人 Powell Matthew R.;Yan Shouli
分类号 G11C27/02 主分类号 G11C27/02
代理机构 代理人
主权项 1. A circuit comprising: a first sample node configured to provide a low precision sample of an input signal; a second sample node configured to store a high precision sample of an input signal; a first switch circuit coupled between an input and the first sample node; and a second switch circuit including bulk material contact area, a first node coupled to the first sample node, a control node responsive to a control signal, and a second node coupled to the second sample node, the bulk material contact area configured to receive a voltage signal configured to reduce current leakage between bulk material and at least one of the first node and the second node during a hold phase.
地址 Austin TX US