INTEGRATED CIRCUIT

摘要

An integrated circuit includes a plurality of first memory cells and a plurality of second memory cells. Each cell of the plurality of first memory cells includes a first inverter, a second inverter, a first pass-gate (PG) transistor and a second PG transistor. Each inverter of the first and second inverters includes a P-type single FinFET transistor and an N-type single FinFET transistor. The first PG transistor and the second PG transistor each are an N-type single FinFET transistor. Each cell of the plurality of second memory cells includes a third inverter, a fourth inverter, a third PG transistor and a fourth PG transistor. Each inverter of the third and fourth inverters includes a P-type single FinFET transistor and an N-type transistor. Each transistor of the third and fourth PG transistors include at least two FinFET transistors electrically coupled in a parallel configuration.

主权项

1. An integrated circuit comprising:
a plurality of first memory cells, each cell of the plurality of first memory cells comprising:
a first inverter;a second inverter, each inverter of the first and second inverters comprising:
a P-type single FinFET (first PU) transistor; andan N-type single FinFET (first PD) transistor;a first pass-gate (PG) transistor; anda second PG transistor, the first PG transistor and the second PG transistor each being an N-type single FinFET transistor;wherein a first X-pitch (X1) of each cell of the plurality of first memory cells extends in a first direction; and a plurality of second memory cells, each cell of the plurality of second memory cells comprising:
a third inverter;a fourth inverter, each inverter of the third and fourth inverters comprising:
a P-type single FinFET (second PU) transistor, andan N-type (second PD) transistor comprising at least two FinFET transistors electrically coupled in a parallel configuration;a third PG transistor, anda fourth PG transistor, each transistor of the third PG transistor and the fourth PG transistor including at least two FinFET transistors electrically coupled in a parallel configuration; andwherein a second X-pitch (X2) of each cell of the plurality of second memory cells extends in the first direction, and X2 being greater than X1.