METHODS AND APPARATUS FOR RUNNING AND BOOTING AN INTER-PROCESSOR COMMUNICATION LINK BETWEEN INDEPENDENTLY OPERABLE PROCESSORS

摘要

Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

主权项

1. Processor apparatus, comprising:
a first digital processor; a physical bus interface in data communication with the first digital processor; and a computer readable medium in data communication with the first digital processor and comprising one or more computer readable instructions, the one or more computer readable instructions configured to, when executed by the first digital processor, cause the first digital processor to transmit a boot stage image to a processing entity via at least the physical bus interface.