| 摘要 |
An arithmetic circuit comprises first to N-th, N being an integer equal to or larger than three, element circuits respectively including: input circuits which input first operand data and second operand data; and element data selectors which select operand data of any of element circuits on the basis of a request element signal; and a data bus which supplies the operand data from the input circuits to the element data selectors. When a control signal is in a first state, the element data selectors select, on the basis of the request element signal included in the second operand data, the first operand data of any of the element circuits and output the first operand data. |
| 主权项 |
1. An arithmetic circuit comprising:
first to N-th, N being an integer equal to or larger than three, element circuits respectively including:
input circuits configured to input first operand data and second operand data; andelement data selectors configured to select operand data of any of element circuits on the basis of a request element signal; and a data bus configured to supply the operand data input by the element circuits from the input circuits of the element circuits to the element data selectors of the element circuits, wherein when a control signal is in a first state, the element data selectors in the first to N-th element circuits respectively select, on the basis of the request element signal included in the second operand data, the first operand data of any of the element circuits and output the first operand data, and the first to N-th element circuits respectively include:
operand selectors configured to select, when the control signal is in a second state, on the basis of element numbers and shift amounts of the element circuits, the first operand data or second operand data and output the selected operand data to the data bus; andadders for element concatenate shift left configured to generate the request element signal on the basis of the element numbers and the shift amounts of the element circuits. |
