发明名称 |
METHOD FOR FORMING AN IMPLANTED AREA FOR A HETEROJUNCTION TRANSISTOR THAT IS NORMALLY BLOCKED |
摘要 |
The invention relates to a method for manufacturing a heterojunction transistor (1), said method comprising the steps of: forming an implanted area (8) by ionically implanting magnesium, calcium, zinc, or fluorine in a first gallium nitride semiconductor layer (4), having a hexagonal crystalline structure, in the [0 0 0 1] orientation of said crystalline structure; forming a second semiconductor layer (6) on the first semiconductor layer so as to form an electron gas layer (5) at the interface between the first and second layers; and forming a control gate (75) over the second conductive layer (6) and vertically in line with the implanted area (8). |
申请公布号 |
US2016104791(A1) |
申请公布日期 |
2016.04.14 |
申请号 |
US201414787623 |
申请日期 |
2014.04.18 |
申请人 |
COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES |
发明人 |
MORVAN Erwan |
分类号 |
H01L29/778;H01L29/20;H01L29/205;H01L29/66;H01L21/265;H01L21/324;H01L21/02;H01L29/04;H01L29/207 |
主分类号 |
H01L29/778 |
代理机构 |
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代理人 |
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主权项 |
1. A heterojunction transistor fabrication process, comprising:
forming an implanted zone by ion implanting magnesium, calcium, zinc or fluorine in a first semiconductor layer of gallium nitride of hexagonal crystal structure in line with the [0001] direction of the crystal structure; forming a second semiconductor layer on the first semiconductor layer so as to form an electron gas layer at an interface between the first and second semiconductor layers; and forming a control gate above the second conductive layer plumb with the implanted zone. |
地址 |
Paris FR |