发明名称 TRANSACTION RESPONSE MODIFICATION WITHIN INTERCONNECT CIRCUITRY
摘要 Interconnect circuitry 10 for connecting transaction masters 4, 6, 8 to transaction slaves 12, 14 includes response modification circuitry 18. The response modification circuitry includes shortlist buffer circuitry 28 storing identification for modification target transaction responses. The response modification circuitry 18 uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry 18 then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master 4, 6, 8.
申请公布号 US2016103776(A1) 申请公布日期 2016.04.14
申请号 US201514874801 申请日期 2015.10.05
申请人 ARM LIMITED 发明人 TUNE Andrew David;LAUGHTON Arthur Brian;SARA Daniel Adam;SALISBURY Sean James;RIOCREUX Peter Andrew
分类号 G06F13/364;G06F15/78;G06F13/42 主分类号 G06F13/364
代理机构 代理人
主权项 1. An apparatus comprising: response modification circuitry to: store identification data for modification target transaction responses in a shortlist buffer;identify, using the identification data stored in the shortlist buffer, a modification target transaction response in a stream of transaction responses in transit from a transaction slave to a transaction master; andmodify the modification target transaction response to form a modified transaction response to be sent to the transaction master.
地址 Cambridge GB