| 摘要 |
A memory device and method of operation, includes latching circuitry 250 for receiving a latching value and passing to an output (Q). A path 230 (or global bitline) receives the latching value, passing to the latching circuitry input. First storage circuitry 210 which may be a bit cell (e.g SRAM, DRAM memory cell etc) provides a first stored value when the device is in a read mode. A bit line 215 (and preferably a precharge circuit 240) is connected to the first storage circuitry 210. A first control circuitry 220 (e.g a bit line multiplexer employing p-type transistors) selectively connects the bit line (or local bitline) to the path 230 (or global bitline). Sensing circuitry 247, on presence of an active enable signal, detects a voltage change on path 230 as a result of connecting the bit line 215 to the first storage circuitry 220 and also to the path 230. The sensing circuitry outputs a latching value which depends on the path voltage change. Second storage circuitry 260 provides a second stored value in a test mode of operation, whilst a second control circuitry (e.g n-type transistor) selectively passes the second stored value to the latching value on the path. The latching circuitry outputs the latching value in dependence on an enable signal which controls both the latching and sense circuits. When the memory device toggles into the test mode, the second stored value will be selected by the second control circuitry, and the test data will bypass the read data. The second storage may be a latch configured to store a test value, and configured to select between a data value and scan input value based on the value of a provided scan signal. The clock to output time for both the test mode and read mode may be within 1.5% of each other. The path may also include a selectable path pre-charge circuit, such that the sensing circuitry detects a voltage change on the path following pre-charging of this node. The path thus has a dynamic evaluation and precharge mode. The memory device supports Design For Test (DFT) and write-through modes. |
