Resistive memory device with word lines coupled to multiple sink transistors

摘要

A resistive memory device includes memory cell array blocks, a reference cell array block, two first and second sink transistors, and a word line. Each of the memory cell array blocks includes a row line, and the reference cell array block includes a reference row line. One of the first sink transistors is disposed between one end of the row line and a ground and the other of the first sink transistors is disposed between an opposite end of the row line and the ground. One of the second sink transistors is disposed between one end of the reference row line and the ground and the other of the second sink transistors is disposed between an opposite end of the reference row line and the ground. The word line is coupled to gates of the first and second sink transistors.

主权项

1. A resistive memory device comprising:
a memory cell array block having a plurality of memory cells and at least one reference cell array block having a plurality of reference cells, wherein each of the memory cell array block and the at least one reference cell array block includes a respective plurality of row lines and a respective plurality of bit lines, each row line intersecting each bit line without being in contact, wherein each bit line is coupled, through each memory cell or reference cell, to each row line at each intersection; a selection unit configured: to select an Mth bit line and an Nth row line from each of the memory cell array block and the at least one reference cell array blocks, and to cause cell current to flow through a selected memory cell that is disposed at a region where the Mth bit line and the Nth row line intersect each other in the memory cell array block and at least one reference current to flow through the at least one reference cell that is disposed at a region where the Mth bit line and the Nth row line intersect each other in the at least one reference cell array blocks; a first sink transistor coupled to an end of the Nth row line of the memory cell array block; a second sink transistor coupled to an opposite end of the Nth row line of the memory cell array block; a third sink transistor coupled to an end of the Nth row line of each of the at least one reference cell array blocks; a fourth sink transistor coupled to an opposite end of the Nth row line of each of the at least one reference cell array blocks; and a word line coupled to a gate of the first sink transistor, a gate of the second sink transistor, a gate of the third sink transistor, and a gate of the fourth sink transistor, wherein the selection unit is further configured to select the word line.