| 发明名称 | Non-volatile memory device | ||
| 摘要 | The invention concerns a memory device comprising: a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data; and a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data; wherein said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration. | ||
| 申请公布号 | US9311994(B2) | 申请公布日期 | 2016.04.12 |
| 申请号 | US201414324110 | 申请日期 | 2014.07.04 |
| 申请人 | Commissariat à l'énergie atomique et aux énergies alternatives;Centre National de la Recherche Scientifique | 发明人 | Di Pendina Grégory;Javerliac Virgile |
| 分类号 | G11C11/00;G11C13/00;G11C11/16;G11C14/00 | 主分类号 | G11C11/00 |
| 代理机构 | Kaplan Breyer Schwarz & Ottesen, LLP | 代理人 | Kaplan Breyer Schwarz & Ottesen, LLP |
| 主权项 | 1. A memory device comprising: a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data and a first data latch coupled to said first resistive element; and a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data and a second data latch coupled to said second resistive element and to said first data latch; wherein said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration; and wherein a data storage node of said first data latch is coupled to an input node of the memory device for receiving an input data signal, and a data storage node of said second data latch is coupled to an output node of the memory device. | ||
| 地址 | FR | ||