| 发明名称 |
Method and apparatus for monitoring general purpose input output, GPIO, signals |
| 摘要 |
An apparatus and method for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC. The apparatus comprises a first checksum generation unit adapted to generate a first checksum on the basis of GPIO bits stored in GPIO registers of the SoC, being connected via corresponding input output, IO, pad circuits to provide analog GPIO signals at the GPIO pins. A second checksum generation unit is adapted to generate a second checksum on the basis of the analog GPIO signals at the GPIO pins representing the GPIO bits. Checker logic is adapted to compare the first checksum generated by the first checksum generation unit with a second checksum generated by the second checksum generation unit. |
| 申请公布号 |
US9311206(B2) |
申请公布日期 |
2016.04.12 |
| 申请号 |
US201414253399 |
申请日期 |
2014.04.15 |
| 申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
Culshaw Carl;Maiolani Mark;Moran Robert F. |
| 分类号 |
H03M13/00;G06F11/30;G11C29/42;G11C29/02;G11C29/04 |
主分类号 |
H03M13/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC, said apparatus comprising:
a first checksum generation unit adapted to generate a first checksum on the basis of GPIO bits stored in GPIO registers of said system on chip, SoC, being connected via corresponding input output, IO, pad circuits to provide analog GPIO signals at the GPIO pins of the GPIO port; a second checksum generation unit adapted to generate a second checksum on the basis of the analog GPIO signals at the GPIO pins of the GPIO port representing the GPIO bits; and a checker logic adapted to compare the first checksum generated by said first checksum generation unit with a second checksum generated by the second checksum generation unit to verify a match between both checksums. |
| 地址 |
Austin TX US |
