Semiconductor storage circuit and operation method thereof

摘要

A semiconductor storage circuit includes a memory core which includes multiple memory cells; an error checking and correction (ECC) encoder; and an ECC decoder. The memory core is activated in response to input of a command for each operation cycle. The ECC encoder performs ECC encoding of input data which is input together with a write command and thus generates ECC data, and generates write data including the input data and the ECC data. The ECC decoder performs ECC decoding of read data which has been read from the memory core according to a read command, using ECC data included in the read data, and thus generates output data. An adjustment is made to equalize a delay from input of a write command until activation of the memory core and a delay from input of a read command until activation of the memory core.

主权项

1. A semiconductor storage circuit comprising:
a memory core including a plurality of memory cells; an error checking and correction (ECC) encoder; and an ECC decoder, wherein the memory core is activated in response to input of a command for an operation cycle, wherein the ECC encoder performs ECC encoding of input data which is input together with a write command and thus generates ECC data, and generates write data including the input data and the ECC data, wherein the ECC decoder performs ECC decoding of read data which has been read from the memory core according to a read command, using ECC data included in the read data, and thus generates output data, wherein an adjustment is made to equalize a delay from input of the write command until activation of the memory core and a delay from input of the read command until activation of the memory core, and wherein the semiconductor storage circuit further comprises one of:
a delay circuit that makes the adjustment by generating a delayed clock by delaying a clock signal which is supplied from outside the semiconductor storage circuit, and supplying the delayed clock to the memory core, the ECC decoder performing the ECC decoding in sync with the delayed clock and a delay time of the delayed clock being set such that activation of the memory core will follow completion of the ECC encoding; anda control circuit that makes the adjustment by generating a control signal for controlling an activation of the memory core, and supplying the control signal to the memory core.