Managing per-tile event count reports in a tile-based architecture

摘要

A graphics processing system configured to track per-tile event counts in a tile-based architecture. A tiling unit in the graphics processing system is configured to cause a screen-space pipeline to load a count value associated with a first cache tile into a count memory and to cause the screen-space pipeline to process a first set of primitives that intersect the first cache tile. The tiling unit is further configured to cause the screen-space pipeline to store a second count value in a report memory location. The tiling unit is also configured to cause the screen-space pipeline to process a second set of primitives that intersect the first cache tile and to cause the screen-space pipeline to store a third count value in the first accumulating memory. Conditional rendering operations may be performed on a per-cache tile basis, based on the per-tile event count.

主权项

1. A graphics processing system configured to track per-tile event counts in a tile-based architecture, the graphics processing system comprising:
a tiling unit configured to:
cause a screen-space pipeline to load a first count value associated with a first cache tile into a count memory,cause the screen-space pipeline to process a first set of primitives that intersect the first cache tile,cause the screen-space pipeline to store a second count value,cause the screen-space pipeline to process a second set of primitives that intersect the first cache tile, andcause the screen-space pipeline to store a third count value, wherein at least one primitive in the first set of primitives and at least one primitive in the second set of primitives cause the screen-space pipeline to detect an event type and increment the count memory.