发明名称 |
Indirect instruction predication |
摘要 |
A method, circuit arrangement, and program product for selectively predicating instructions in an instruction stream by determining a first register address from an instruction, determining a second register address based on a value stored at the first register address, and determining whether to predicate the instruction based at least in part on a value stored at the second register address. Predication logic may analyze the instruction to determine the first register address, analyze a register corresponding to the first register address to determine the second register address, and communicate a predication signal to an execution unit based at least in part on the value stored at the second register address. |
申请公布号 |
US9311090(B2) |
申请公布日期 |
2016.04.12 |
申请号 |
US201313779189 |
申请日期 |
2013.02.27 |
申请人 |
International Business Machines Corporation |
发明人 |
Muff Adam J.;Schardt Paul E.;Shearer Robert A.;Tubbs Matthew R. |
分类号 |
G06F9/35;G06F9/30 |
主分类号 |
G06F9/35 |
代理机构 |
Middleton Reutlinger |
代理人 |
Middleton Reutlinger |
主权项 |
1. A circuit arrangement, comprising:
a processing unit; a first register disposed in the processing unit; an execution unit disposed in the processing unit and configured to receive a predication enable signal that indicates whether to predicate an instruction and selectively predicate instructions based at least in part on the predication enable signal; predication logic disposed in the processing unit and configured to receive a first register address corresponding to the first register included in the instruction, determine a second register address based at least in part on a value stored at the first register address of the first register, and communicate the predication enable signal based at least in part on a value stored at the second register address; and instruction decoding logic configured to decode an instruction including a first register address, determine whether the instruction is of a type that supports predication, and communicate the first register address and a predication valid signal indicating whether the instruction is of a type that supports prediction to the predication logic, wherein the predication logic is configured to receive a first register address corresponding to the first register included in a decoded instruction, determine a second register address based on a value stored at the first register address of the first register, and communicate the predication enable signal based at least in part on a value stored at the second register address responsive to receiving the predication valid signal indicating that the instruction is of the type that supports predication. |
地址 |
Armonk NY US |