System with feature of saving dynamic power of flip-flop banks

摘要

A system comprises a first plurality of flip-flop circuits, a second plurality of flip-flop circuits, and a gating control module. At a first processor frequency, gating of clock signals is enabled for the first and second plurality of flip-flop circuits. At a second processor frequency, gating of a first of the clock signals is disabled for the first plurality of flip-flop circuits and gating of a second of the clock signals is enabled for the second plurality of flip-flop circuits.

主权项

1. A system comprising:
a first plurality of flip-flop circuits associated with a first threshold frequency above which a setup time requirement for the first plurality of flip-flop circuits is not met; a second plurality of flip-flop circuits associated with a second threshold frequency above which a setup time requirement for the second plurality of flip-flop circuits is not met; and a gating control module operable to:
enable gating of clock signals for the first and second plurality of flip-flop circuits in response to operation of a processor of the system at a first processor frequency that is below both the first threshold frequency and the second threshold frequency, wherein
the gating control module is configured to:
receive an indicator of the first processor frequency,compare the indicator of the first processor frequency to an identifier of the first threshold frequency at or below which gating can be enabled for the first plurality of flip-flop circuits, andset a first gating enable signal for the first plurality of flip-flop circuits based on whether the identifier of the first threshold frequency is higher than the indicator of the first processor frequency; and disable gating of a first of the clock signals for the first plurality of flip-flop circuits in response to operation of the processor at a second processor frequency that is above the first threshold frequency and enable gating of a second of the clock signals for the second plurality of flip-flop circuits in response to the second processor frequency being below the second threshold frequency.