Memory timing self-calibration

摘要

Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes sequentially programming a plurality of delay trim settings into a delay circuit of a data path. The data path can include a data latch coupled to the delay circuit. A clock is coupled to the data latch to clock data into the data latch. Transitions of the data are substantially aligned with transitions of the clock. An output of the data latch is read after each delay trim setting is programmed. A boundary is determined between a first output state of the data latch and a second output state of the data latch wherein the boundary is associated with a particular delay trim setting of the plurality of delay trim settings. The particular delay trim setting is programmed into the delay circuit.

主权项

1. A method comprising:
sequentially programming a plurality of delay trim settings into a delay circuit of a data path comprising a data latch coupled to the delay circuit and a clock configured to clock data into the data latch, wherein transitions of the data are substantially aligned with transitions of the clock; determining a boundary between a first output state of the data latch and a second output state of the data latch, the boundary associated with a particular delay trim setting of the plurality of delay trim settings; and programming the particular delay trim setting into the delay circuit.