Hardware implemented ethernet multiple tuple filter system and method

摘要

A filter in a DOCSIS bridge performs IP Filtering of incoming Ethernet packets in hardware. The filter includes a parser circuit which, in hardware, parses each of the incoming Ethernet packets and then utilizes the parsed information in combination with a content-addressable memory (CAM) that stores filtering information, to filter and route the incoming Ethernet packets. Detailed statistical data may also be generated to provide information on the type of filtering being performed by the DOCSIS bridge.

主权项

1. An electronic device, comprising:
a specialized content addressable memory configured to store filter information that is utilized in filtering upstream and downstream Ethernet frames; a downstream bridge circuit coupled to the specialized content addressable memory, the downstream bridge circuit including hardware circuitry operable to parse downstream Ethernet frames to obtain parsed information from these downstream Ethernet frames and to route and filter the downstream Ethernet frames based on this parsed information and the filter information stored in the specialized content addressable memory; an upstream bridge circuit coupled to the specialized content addressable memory, the upstream bridge circuit including hardware circuitry operable to parse upstream Ethernet frames to obtain parsed information from these upstream Ethernet frames and to route and filter the upstream Ethernet frames based on this parsed information and the filter information stored in the specialized content addressable memory; and wherein the downstream bridge circuit includes a downstream IP filter implemented entirely in hardware circuitry, the downstream IP filter configured to filter and route the downstream Ethernet frames based on the contents of fields extracted from the Ethernet frames and from higher level packets encapsulated in the Ethernet frames, and on the filter information stored in the specialized content addressable memory.