Techniques for memory de-duplication in a virtual system

摘要

Techniques for memory de-duplication in a virtual system are described. An apparatus may comprise a first processor circuit coupled to a second processor circuit. A memory unit may be coupled to the first processor circuit and the second processor circuit, the memory unit to store private memory pages and shared memory pages for multiple virtual machines. A memory management application may be operative on the first processor circuit and the second processor circuit in a shared manner to perform memory de-duplication operations on the private memory pages stored in the memory unit to form shared memory pages. The memory management application may perform sequential memory de-duplication operations on the first processor circuit, and parallel memory de-duplication operations on the second processor circuit. Other embodiments are described and claimed.

主权项

1. An apparatus, comprising:
a first processor circuit; a second processor circuit coupled to the first processor circuit; a memory unit coupled to the first processor circuit and the second processor circuit, the memory unit to store private memory pages and shared memory pages for multiple virtual machines; a memory management application operative on the first processor circuit and the second processor circuit to perform memory de-duplication operations on the private memory pages stored in the memory unit to form shared memory pages, the memory management application to perform sequential memory de-duplication operations on the first processor circuit and parallel memory de-duplication operations on the second processor circuit, the first processor circuit capable of executing a sequential operation more quickly than the second processor circuit, and the second processor circuit capable of executing a parallel operation more quickly than the first processor circuit; a page nomination component operative on the first processor circuit to nominate a set of candidate memory pages suitable for a shared memory page based on a set of selection criteria as at least one of the sequential memory de-duplication operations; a page compare component operative on the second processor circuit to compare a characteristic of at least two of the candidate memory pages to identify identical memory pages as at least one of the parallel memory de-duplication operations; and a last level cache coupled to the first processor circuit and the second processor circuit, the page nomination component to provide indications of the candidate memory pages to the second processor circuit via the last level cache, and the page compare component to provide indications of the identical memory pages to the first processor circuit via the last level cache.