Circuits for and methods of filtering inter-symbol interference for SerDes applications

摘要

A circuit for filtering inter-symbol interference in an integrated circuit is described. The circuit comprises a first stage coupled to receive digital samples of an input signal. The first stage generates first decision outputs based upon the digital samples. A second stage is coupled to receive the digital samples of the input signal. The second stage comprises a filter receiving the first decision outputs and generating second decision outputs based upon the digital samples of the input signal and detected inter-symbol interference associated with the first decision outputs. A method of filtering inter-symbol interference in an integrated circuit is also described.

主权项

1. A circuit for filtering inter-symbol interference in an integrated circuit, the circuit comprising:
a first stage coupled to receive digital samples of an input signal, wherein the first stage generates first decision outputs based upon the digital samples of the input signal; and a second stage coupled to receive the digital samples of the input signal; wherein the second stage comprises a pre-filter coupled to an output of a delay element for receiving delayed digital samples, and a filter receiving the first decision outputs and generating filtered decisions, the delay element aligning an output of the pre-filter with the filtered decisions; and wherein the second stage generates second decision outputs based upon the digital samples of the input signal that are filtered before inter-symbol interference cancellation and detected inter-symbol interference associated with the first decision outputs.