High-speed I/O data system

摘要

In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates an NRZ data signal, and a clock channel communicates a forwarded clock signal, from the data transmission system to the data reception system. The data transmission system includes a first differential serializing transmitter to generate the NRZ data signal from pulsed data, and further includes a second differential serializing transmitter to generate a forwarded clock signal. A first multi-phase transmit clock generator generates transmit clock signals for the first and second differential serializing transmitters. The data reception system includes a data receiver and a de-serializer to receive and de-serialize the NRZ data signal, and includes a multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver.

主权项

1. A system, comprising:
a differential serializing transmitter configured to output non-return-to-zero (NRZ) data that is generated from pulsed data, the differential serializing transmitter comprising a first M:1 pulse-generating multiplexer configured to generate a first output as a series of intermediate pulses having a first pulse width, the first output configured as a first input to a pulse-controlled push-pull output driver; and a first computer chip comprising a data transmitter that includes the differential serializing transmitter and a serializer configured to input data signals and multi-phase clock signals to the differential serializing transmitter.