Phase lock loop (PLL/FLL) clock signal generation with frequency scaling to power supply voltage

摘要

A clock signal generation circuit provides an output clock signal to a digital system. The digital system is powered by a power supply voltage, VDD, that may include transients associated with the impedance of the packaged digital system. The clock signal generation circuit dynamically scales an output clock frequency based on monitored changed to VDD. The output clock frequency may be selected to approximate a maximum (margin-less) system Fmax for the monitored VDD. The average clock frequency may be improved compared with operating at a fixed output clock frequency.

主权项

1. A method of operating a PLL/FLL clock generation circuit, comprising:
providing an output clock signal to a digital system; monitoring changes to a level of a power supply voltage VDD that is provided to the digital system to produce measured VDD changes; generating a fractional adjustment signal based on the measured VDD changes; and dynamically adapting a frequency of the output clock signal of the PLL/FLL clock generation circuit by a divider that receives the output clock signal and the fractional adjustment signal.