VIRUS CO-PROCESSOR INSTRUCTIONS AND METHODS FOR USING SUCH

摘要

Circuits and methods for detecting, identifying and/or removing undesired content are provided. According to one embodiment, a virus processing system includes a virus co-processor, a first memory, a general purpose processor (GPP) and a second memory. The first memory is communicably coupled to the co-processor via a first memory interface. The first memory includes a first signature compiled for execution on the co-processor. The GPP is communicably coupled to the co-processor. The second memory is communicably coupled to the co-processor via a second memory interface and to the GPP. The second memory includes a second signature compiled for execution on the GPP. The co-processor is operable to retrieve the first signature stored within the first memory through an instruction cache. The co-processor is operable to retrieve a data segment to be scanned from second memory through a data cache that is separate from the instruction cache.

主权项

1. A virus processing system, the virus processing system comprising:
a virus co-processor; a first memory associated with the virus co-processor and communicably coupled to the virus co-processor via a first memory interface, wherein the first memory includes a first virus signature compiled for execution on the virus co-processor; a general purpose processor, wherein the general purpose processor is communicably coupled to the virus co-processor; a second memory associated with the general purpose processor and communicably coupled to the virus co-processor via a second memory interface and to the general purpose processor, wherein the second memory includes a second virus signature compiled for execution on the general purpose processor; and wherein the virus co-processor is operable to retrieve the first virus signature stored within the first memory through an instruction cache; and wherein the virus co-processor is operable to retrieve a data segment to be scanned for viruses stored within the second memory through a data cache; and wherein the instruction cache and the data cache are separate.