HIGH BREAKDOWN VOLTAGE LDMOS DEVICE

摘要

A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).

主权项

1. A method for forming a multi-gate lateral-diffused-metal-oxide-semiconductor (LDMOS) device having a centrally located LDMOS region and a peripherally located LDMOS region, comprising:
providing a semiconductor-on-insulator (SOI) structure comprising a dielectric layer overlain by a first semiconductor layer of a first conductivity type; forming a second semiconductor layer over the first semiconductor layer; forming the centrally located and the peripherally located LDMOS region substantially in or on the second semiconductor layer; and forming a deep trench isolation (DTI) region in the first and second semiconductor layers, the DTI region extending to the dielectric layer and laterally bounding the peripherally located LDMOS region.