SYSTEM FOR ELECTRICAL TESTING AND MANUFACTURING OF A 3-D CHIP STACK AND METHOD

摘要

A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.

主权项

1. A method for electrical testing of a 3-D integrated circuit chip stack comprising at least a first integrated circuit chip and a second integrated circuit chip, wherein the first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing, the method comprising:
placing an integrated circuit chip holder on an integrated circuit chip carrier, wherein the integrated circuit chip carrier is operable for electrically connecting the 3-D chip stack with an electronic testing system; making a first temporary electrical connection between the first integrated circuit chip and the integrated circuit chip carrier and a first temporary mechanical connection between the first integrated circuit chip and the integrated circuit chip carrier, wherein the integrated circuit chip holder is operable for making the first temporary electrical connection and the first temporary mechanical connection; making a second temporary electrical connection between the second integrated circuit chip and the first integrated circuit chip and a second temporary mechanical connection between the second integrated circuit chip and the first integrated circuit chip, wherein the integrated circuit chip holder is operable for making the second temporary electrical connection and the second temporary mechanical connection; and performing electrical testing of the 3-D integrated circuit chip stack using the electrical testing system.