PAGE BUFFER CIRCUIT FOR NAND FLASH MEMORY

摘要

A page buffer for a NAND flash memory array includes a pre-charge switch, a first switch, a read switch, a write switch, a latch, and a data switch. The pre-charge switch is coupled between a supply node with a supply voltage and a bit line that is coupled to a selected cell of the NAND flash memory array. The first switch is coupled between the bit line and a data node. The read switch is coupled between the data node and an I/O node. The write switch is coupled between an inverse data node, which is out of phase with the data node, and the I/O node. The latch is coupled between the data node and the inverse data node. The data switch is coupled between the inverse data node and a first node. The enable switch is coupled between the first node and a ground.

主权项

1. A page buffer for a NAND flash memory array, comprising:
a pre-charge switch, coupled between a supply node and a bit line and controlled by a pre-charge signal, wherein the bit line is coupled to a selected cell of the NAND flash memory array, and the supply voltage is applied to the supply node; a first switch, coupled between the bit line and a data node and controlled by a program signal; a read switch, coupled between the data node and an I/O node and controlled by a read signal; a write switch, coupled between an inverse data node and the I/O node and controlled by a write signal, wherein the data node and the inverse data node are out of phase; a latch, coupled between the data node and the inverse data node; a data switch, coupled between the inverse data node and a first node and controlled by the bit line; and an enable switch, coupled between the first node and a ground and controlled by an enable signal.