Leakage-Current Abatement Circuitry for Memory Arrays

摘要

In one memory array embodiment, in order to compensate for bit-line leakage currents by OFF-state bit-cell access devices, a leakage-current reference circuit tracks access-device leakage current over different process, voltage, and temperature (PVT) conditions to generate a leakage-current reference voltage that drives a different leakage-current abatement device connected to each different bit-line to inject currents into the bit-lines to compensate for the corresponding leakage currents. In one implementation, the leakage-current reference circuit has a device that mimics the leakage of each access device configured in a current mirror that drives the resulting leakage-current reference voltage to the different leakage-current abatement devices.

主权项

1. An integrated circuit comprising
a memory array that comprises:
one or more sub-arrays, each sub-array comprising a plurality of bit-cells, arranged in rows and columns, the bit-cells of each column in each sub-array being coupled to least one bit-line;at least one bit-line leakage-current abatement element coupled with each bit- line and configured to inject a current into that bit-line, responsive to a leakage-current reference; anda bit-line leakage-current reference circuit, configured to generate the leakage- current reference and to provide the generated leakage-current reference to the at least one respective bit-line leakage-current abatement element coupled with that bit-line.