THERMAL-AWARE COMPILER FOR PARALLEL INSTRUCTION EXECUTION IN PROCESSORS

摘要

Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.

主权项

1. A method for compiling instruction code for execution in a processor having a plurality of functional units, comprising:
determining a thermal constraint of the processor; and scheduling in the compiled instruction code real instructions to be executed in parallel by the plurality of functional units, wherein said scheduling is configured to prevent exceeding the thermal constraint during execution of the instruction code.