DECIMAL AND BINARY FLOATING POINT ROUNDING

摘要

Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.

主权项

1. A logic device comprising:
an arithmetic logic circuitry for performing a floating point arithmetic add/subtract operation on a first floating point number and a second floating point number, the first floating point number having a first magnitude and the second floating point number having a second magnitude, and the first and second floating point numbers being both in decimal or binary floating point format, wherein the arithmetic logic circuitry is configured to implement a method comprising:
in case of the floating point numbers being in binary floating point format, mapping the binary floating point numbers to decimal floating point format, the mapping comprising padding bits to form digits that share the same fields of the floating point numbers in the decimal floating point format;generating a guard digit of zero of at least one of the first or the second floating point numbers by transforming the first and the second floating point numbers by a compressing function;determining as a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and a first difference or a second difference of the transformed floating point numbers, wherein for the first difference the second floating point number is subtracted from the first floating point number and for the second difference the first floating point number is subtracted from the second floating point number, and determining a corresponding result plus one by additionally adding a value of one to the result;generating injection values for rounding a final result in dependence of the first and second floating point numbers being in decimal floating point format or binary floating point format, of a rounding mode and of the arithmetic operation;generating injection carry values based on the transformed first and second floating point numbers and the injection values; andselecting the final result from the result, the result plus one and a least significant digit based on the injection carry values and end around carry signals.