SIGNAL DELAY FLIP-FLOP CELL FOR FIXING HOLD TIME VIOLATION

摘要

A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.

主权项

1. An integrated circuit (IC) comprising:
logic cells; and flip-flop cells connected with the logic cells in a combination in a functional mode of operation, and connected together in series in a scan test mode of operation by a scan control signal for shifting scan test data into the IC, a signal delay cell provided by at least one of the flip-flop cells, wherein the signal delay cell has a first multiplexer having a first data input node, a scan data input node and a first output node, a second multiplexer having a second data input node, a second input node connected to the first output node, and a second output node, and a flip-flop module having a data input connected to the second output node, a clock input node and a flip-flop output node, and wherein the propagation of a scan data input signal applied to the scan data input node in the scan test mode of operation is delayed, and the hold margin of the flip-flop module for the scan data input signal is increased by transit through the first multiplexer.