| 摘要 |
Disclosed is a cache logic that generates cache addresses from an input memory address split into two binary strings. The cache logic has a hashing engine that generates a third binary string from the first binary string by combining subsets of bits of the first binary string by means of a bitwise operation, the subsets of bits are defined at the hashing engine such that each subset is unique and is made up of about half of the bits of the first binary string. The cache logic also has a combination unit that combines the third binary string with the second binary string by means of a reversible operation to form a binary output string for use as part of a cache address in a cache memory. The subsets of bits may be defined in hardware as data paths. The hashing engine may include sets of bitwise operators that form a bit of the third string from the corresponding subset of bits of the first string. |
