| 摘要 |
Disclosed is a processor with a common supply rail, and some processor cores that share the common supply rail. Each of the cores output a core dIPC value and receives as an input a core throttling signal. The processor has a chip power management logic 301 which has inputs 302 - 309 for the dIPC values, a threshold register 334 for a dIPC threshold value, chip dIPC register 319 to hold a current global dIPC value based on the average of the core values, and dIPC history registers 320 - 327 holding historic global values with an average historic global value stored in a register 331. There is a subtraction unit 332 to provide an absolute difference of an average historic global dIPC value based on the historic global dIPC value and the current dIPC values. A magnitude comparator 333 provides a throttling signal when the absolute difference is above the dIPC threshold value, which is output 310 - 317 to the processor cores. |
