发明名称 |
An integrated level shifting latch circuit and method of operation of such a latch circuit |
摘要 |
An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry. |
申请公布号 |
GB2512993(B) |
申请公布日期 |
2016.04.06 |
申请号 |
GB20140002612 |
申请日期 |
2014.02.14 |
申请人 |
ARM LIMITED |
发明人 |
GUS YEUNG;BO ZHENG;FRANK GUO |
分类号 |
G11C7/10;H03K3/012;H03K3/356;H03K19/0185 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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